The present invention relates to a semiconductor memory device; and, more particularly, to a delay locked loop (DLL) circuit for use in a semiconductor memory device.
In a system having a plurality of semiconductor devices that perform a variety of functions, a semiconductor memory device is a device for storing data. This semiconductor memory device outputs data corresponding to an address from a data processing device, for example, a central processing unit to a device requesting such data, or stores data transmitted from the data processing device in a unit cell of the semiconductor memory device corresponding to an address inputted along with the data.
As an operating speed of system becomes faster, a data input/output speed of a semiconductor memory device required by a data processing device provided in the system becomes faster. Moreover, due to the recent rapid advance of semiconductor integrated technology, the operating speed of the data processing device is faster, but the data input/output speed of the semiconductor memory device that communicates data with the data processing device does not follow the increasing speed of the data processing device.
In order to increase the data input/output speed of the semiconductor memory device to the level required by the data processing device, various types of semiconductor memory devices have been developed. One of the most widely used semiconductor memory devices up to now has been a synchronous memory device incorporating a data processing device therein, which allows data output every period of a system clock. Such a synchronous memory device accepts a system clock and outputs data to the data processing device corresponding to the period of the system clock inputted thereto or takes data from the data processing device every period of the system clock. However, even the synchronous memory device does not run after the operating speed of the data processing device, and thus, DDR synchronous memory device has been proposed. The DDR synchronous memory device outputs or receives data each time a system clock is transited. That is, it receives or outputs data in synchronism with each of rising transition and falling transition.
However, the system clock inputted to the memory device arrives in a data output circuit with a certain delay inevitably caused due to a clock input buffer arranged in the memory device, transmission lines for transmitting the clock signal, and the like. Thus, if the data output circuit outputs data in synchronism with the system clock that is transmitted with a certain delayed time already occurred, an external device will receive the data, which is not synchronized with the rising edge and falling edge of the system clock, outputted from the memory device.
To solve the above problem, a semiconductor memory device is provided with a DLL circuit for locking a delay of a clock signal. The DLL circuit is a circuit for compensating a value delayed by internal circuits of the memory device from input of the system clock to the memory device to its delivery to a data output circuit. This DLL serves to find a delayed time due to the clock input buffer of the semiconductor memory device, clock signal transmission lines and the like, and delays the system clock corresponding to the found value and then outputs the same to the data output circuit. In other words, by the DLL circuit, the system clock inputted to the memory device is delivered to the data output circuit in a state that the delayed value is constantly locked. Then, the data output circuit outputs the data in synchronism with the delay locked clock and it is regarded in the outside that the data is outputted precisely in synchronism with the system clock.
Actually, the delay locked clock is outputted from the DLL circuit at a given time faster than the output time of the data by one period and delivered to the output buffer, and the data is outputted in synchronism with the delay locked clock delivered. Thus, the data can be outputted rapidly by the delay of the system clock caused by the internal circuits of the memory device. By doing so, outside of the memory device, it is regarded that the data is outputted precisely in synchronism with each of the rising edge and falling edge of the system clock inputted to the memory device. As a result, the DLL circuit can effectively compensate the delayed value of the system clock caused in the memory device by finding the speed at which the data is to be outputted.
Meanwhile, the delay locked operation of the DLL circuit is divided into a normal delay locked operation and a fine delay locked operation. The normal delay locked operation is to adjust the delay locked value of the system clock depending on the number of unit delay elements through which the system clock is passed. On the other hand, the fine delay locked operation adjusts the number of unit delay elements by more finely adjusting the delayed value of the delay locked clock to the possible range.
However, there is still a need for an improved DLL circuit capable of finely adjusting a system clock depending on a change in a locking state.